Flat cathode ray tube (CRT) displays include displays which exhibit a large aspect ratio (e.g., 10:1 or greater) with respect to conventional deflected-beam CRT displays, and which display an image in response to electrons striking a light emissive material. The aspect ratio is defined as the diagonal length of the display surface to the display thickness. The electrons which strike the light emissive material can be generated by various devices, such as by field emitter cathodes or thermionic cathodes. As used herein, flat CRT displays are referred to as flat panel displays.
Conventional flat panel displays typically include a faceplate structure and a backplate structure which are joined by connecting walls around the periphery of the faceplate and backplate structures. The resulting enclosure is usually held at a vacuum pressure. To prevent collapse of the flat panel display under the atmospheric pressure, a plurality of spacers are typically located between the faceplate and backplate structures at a centrally located active region of the flat panel display.
The faceplate structure includes an insulating faceplate (typically glass) and a light emitting structure formed on an interior surface of the insulating faceplate. The light emitting structure includes light emissive materials, or phosphors, which define the active region of the display. The backplate structure includes an insulating backplate and an electron emitting structure located on an interior surface of the backplate. The electron emitting structure includes a plurality of electron-emitting elements (e.g., field emitters) which are selectively excited to release electrons. The light emitting structure is held at a relatively high positive voltage (e.g., 200 V to 10 kV) with respect to the electron emitting structure. As a result, the electrons released by the electron-emitting elements are accelerated toward the phosphor of the light emitting structure, causing the phosphor to emit light which is seen by a viewer at the exterior surface of the faceplate (the "viewing surface").
FIG. 1 is a schematic representation of the viewing surface of a flat panel display 50. The faceplate structure of flat panel display 50 includes a light emitting structure which is arranged in a plurality of rows of light emitting elements (i.e., pixel rows), such as pixel rows 1-31. Flat panel display 50 typically includes hundreds of pixel rows, with each row typically including hundreds of pixels.
The electron emitting structure of flat panel display 50 is arranged in rows of electron emitting elements which correspond with the pixel rows 1-31 of the faceplate structure. Each row of electron emitting elements includes electron emitting elements which correspond to each of the pixels on the light emitting structure. The electron emitting elements are activated, thereby causing electrons to be transmitted to the corresponding pixels to create an image at the viewing surface of the flat panel display 50.
Spacer walls 41-43 are located between the faceplate structure and the backplate structure. Pixel rows 1-31 and spacers walls 41-43 are greatly enlarged in FIG. 1 for purposes of illustration. It is desirable for spacers 41-43 to extend horizontally across display 50 in parallel with pixel rows 1-31. Spacer wall 41 is illustrated as a properly positioned spacer wall. Spacer wall 41 is perfectly located between pixel rows 8 and 9, such that the spacer wall 41 does not obstruct any of the pixels in pixel rows 8 and 9. While spacer wall 41 illustrates the ideal positioning of a spacer wall, spacer walls 42 and 43 illustrate the positioning which results from conventional methods. Spacer wall 42, although straight, is not located perfectly in parallel with pixel rows 16 and 17. As a result, spacer wall 42 obstructs pixels near the ends of pixel rows 16 and 17. The obstructed pixels will not receive the intended electrons from the electron emitting structure, thereby resulting in degradation of the image viewed by the user. Spacer wall 43 exhibits a waviness which may be inherent in the material used to make the spacer wall 43. Spacer wall 43 therefore obstructs pixels throughout pixel rows 24 and 25, again degrading the image seen by the viewer. Spacer walls 41-43 can also be positioned in a non-perpendicular manner between the faceplate and backplate structures. Such a non-perpendicular positioning can result in the undesirable deflection of electrons. This electron deflection can also degrade the image seen by the viewer.
Consequently, it is desirable to have spacer walls which are precisely aligned within the flat panel display. However, the relatively small size of the spacer walls 41-43 makes it difficult to position these spacer walls 41-43 between the faceplate and backplate structures. Even if the spacer walls 41-43 are initially aligned properly, these spacer walls 41-43 can subsequently shift out of alignment during normal operation of the flat panel display. This shifting may occur as a result of heating or physical shock experienced by the flat panel display.
Spacer walls 41-43 can include face electrodes which are used to control the voltage distribution between the faceplate and backplate structures adjacent to the spacers 41-43. Predetermined external voltages are applied to the face electrodes to control this voltage distribution. It is often difficult to make an electrical connection between these face electrodes and either the faceplate structure and the backplate structure, such that the external voltages can be applied to the face electrodes.
It would therefore be desirable to have a spacer structure which is easy to locate between a faceplate structure and a backplate structure. It would also be desirable if this spacer would remain in precise alignment after assembly of the flat panel display, even in view of exposure to thermal cycling and physical shock. It would further be desirable if such a spacer facilitated easy connection of face electrodes to the faceplate and/or backplate structures.